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KNH's avatar
KNH
Icon for New Contributor rankNew Contributor
10 months ago

Agilex 5 LVDS Electrical Idle

Hello,

Is there any way to dynamically force a pair of Agilex 5 (E-series) LVDS output pins to electrical idle/tri-state/floating (i.e. no differential voltage)? AN-635 describes a forceelecidle port option in the PHY for older devices, but nothing for Agilex 5 regarding either OOB signalling or electrical idle. I believe I can manually instantiate a differential I/O buffer with an output enable, but do I lose access to that enable if I am using the PHY IP in PCS-PMA direct mode?

This is for the purposes of a SATA host controller. The OOB signaling requires that the TX pin pair is held at 0 differential voltage between bursts.

Thank you

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8 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    10 months ago

    Hi,
    related to SATA, I read in most recent GTS Transceiver User Guide that PMA direct mode basically supports SATA protocol (paragraph 2.1 Building Blocks, Table 2) but not yet in latest Quartus version 25.1. "SATA mode is not supported in the current release of the Quartus® Prime Pro Edition software."

    SATA support is also claimed in Architecture Brief Agilex™ 5 FPGAs: High-Speed Serial Interface (HSSI) Hard IP

    GTS PHY has dedicated high speed differential I/O, no way to "instantiate" other I/O hardware.

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    9 months ago

    Hello,


    Any updates on this issue? Does the answer provide helps you move forward? Or do you need more support on this?



    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      9 months ago
      There is a simple open question: When will promised SATA hard IP for Agilex 5 be avaible? Any schedule?
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    9 months ago

    I checked with the internal team and been informed that we support SATA at 1.5G, 3G, 6G, but there is no hard IP. Let me know if you need more details.


  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    9 months ago

    Hi,
    thanks for checking SATA state. Questioned SATA Hard IP is probably a misunderstanding of quoted "High-Speed Serial Interface (HSSI)
    Hard IP" architecture brief.

    Open point is, when will SATA support be available at all. According to most recent Quartus 25.1 doc, it's not yet supported.

    Regards

    Frank

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    9 months ago

    Hello Frank,


    I was informed that the User Guide for SATA for Agilex 5 is still in progress, and the Quartus release is tentatively planned to be around 25.1.1, subject to change.


    Regards,

    Aqid


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    8 months ago

    I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.