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KKlei5's avatar
KKlei5
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1 year ago

Agilex 5 design using DDIO shows clock routing failures

I have a simple design, trying to control some output pins using the Agilex 5 and GPIO Intel FPGA IP. The design is targeted for a new board design, but its so simple this could be done with the Ag...
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ShengN_altera's avatar
ShengN_altera
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11 months ago

Hi,


May I know do you have any further concern?


Thanks,

Regards,

Sheng


  • KKlei5's avatar
    KKlei5
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    11 months ago

    I don't have a clear answer yet, but I did get from Intel/Altera that the Agilex 5 has some limitations not present in previous CyclonV, Arria10 or Stratix10.

    Engineering confirmed the restriction of one single clock source for a byte/lane. This is a hardware restriction and needs to be followed. Given this, all the DDIOs located in a byte/lane should have only one clock source, even if they belong to another GPIO IP instantiation. I am waiting for feedback on the documentation part.