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KKlei5's avatar
KKlei5
Icon for New Contributor rankNew Contributor
1 year ago

Agilex 5 design using DDIO shows clock routing failures

I have a simple design, trying to control some output pins using the Agilex 5 and GPIO Intel FPGA IP. The design is targeted for a new board design, but its so simple this could be done with the Ag...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Have you try with Advanced Fitter Settings:

Final Placement Optimizations Always

Fitter Aggressive Routability Optimizations Always

Physical Placement Effort Optimize for Routability


Optimization Mode: options under Routability


Use different seed. Different seed will have different routing and placement.


Thanks,

Regards,

Sheng