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KKlei5's avatar
KKlei5
Icon for New Contributor rankNew Contributor
1 year ago

Agilex 5 design using DDIO shows clock routing failures

I have a simple design, trying to control some output pins using the Agilex 5 and GPIO Intel FPGA IP. The design is targeted for a new board design, but its so simple this could be done with the Ag...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

Are you using the HPS? It looks like you are. How do you have the I/O peripherals set up in the HPS parameter editor? It also looks like you've created pin assignments in the Pin Planner. Is that where you've made DDIO assigments?