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Altera_Forum's avatar
Altera_Forum
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13 years ago

Afraid of integers and variables...

Hi, I'm still learning a lot about VHDL and I have this question (and it may sound stupid :p). I have the feeling that using variables in VHDL is not good. Maybe because it's confusing in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Maybe it helps if people keep in mind, that all code written is at first processed in a piece of software namly the synthesis software. Variables can help to control this software, define complex cases und structures as eg dynamic code to drive the software to finally generate that what is really needed: objects, structures and .... SIGNALS! If one can write the code without variables using just signals (wich is the case in 99% of the designs) there is no necessarity to invent them.