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Altera_Forum's avatar
Altera_Forum
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13 years ago

Afraid of integers and variables...

Hi,

I'm still learning a lot about VHDL and I have this question (and it may sound stupid :p).

I have the feeling that using variables in VHDL is not good. Maybe because it's confusing in translating it into logic, I don't know.

Also, I never use bool because why would I? It seems more logic (both literally and figuratively) to me to use std_logic.

The same happens when using numbers. I don't use integer, I use unsigned. I have the feeling that I don't control integer... how much logic will it use? I know, you could range the integer, but still...

So I end up using a lot of std_logic, std_logic_vector and unsigned.

Today, I could really use an integer variable. Is there a reason why I shouldn't use it? Am I wrong to think that variables and integers are bad?

Thanks!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I hate variables because they're often unnecessary(you can do it just as easy with a signal) and it's hard to understand how something is going to get synthesized. I've seen them blow up due to misunderstandings. That being said, I knew an excellent hardware engineer who used variables all the time without problem. I think they're most dangerous when writing purely for the function you want with no understanding of what the actual hardware will look like.

    Also, I have run into occasions where variables really were the best way to get the job done and made the most sense. When I looked at what was synthesized, the size and speed was pretty good, and better than I expected.

    As for integers, I think they're a nicety for readability. But I probably do the same thing, trying to code what the hardware looks like, rather than the algorithm.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Maybe it helps if people keep in mind, that all code written is at first processed in a piece of software namly the synthesis software. Variables can help to control this software, define complex cases und structures as eg dynamic code to drive the software to finally generate that what is really needed: objects, structures and .... SIGNALS! If one can write the code without variables using just signals (wich is the case in 99% of the designs) there is no necessarity to invent them.