Honored ContributorI am working on a PCB that is using an Cyclone III FPGA that is connecting to many ADCs and DACs in parallel. The ADC/DAC peripherals are all SPI devices and I want to interface with them at 150MHz to 200MHz. What gotchas should I be aware of? What are best practices are recommended? Advice from veteran designers would be appreciated.
Honored ContributorYou say you have SPI devices and you "want to interface with them at 150MHz to 200MHz". However, its not up to you, it's up to the devices :)
I have never heard of the SPI bus operating at this clock speed. Do you happen to have part numbers you can reference? If you need to have a single FPGA that interfaces to multiple high-speed ADCs and DACs, I would recommend considering using an FPGA with SERDES interfaces, and using those to interface to ADCs/DACs that use the JEDEC JESD204A standard, i.e., http://en.wikipedia.org/wiki/jesd204 NXP has parts, as do other vendors. http://www.nxp.com/campaigns/fasttrackyourdesign/index.php?sub=cgv What sampling frequency were you expecting to operate these devices at? Cheers, DaveHonored ContributorThanks for the great info. I will do some reading on that IO spec you recommend. I had a feeling that SPI could not handle the speed I wanted which is what prompted me to ask. I do not have any part numbers right now as I am still choosing parts.
Honored ContributorHow many ADCs/DACs do you need to interface to, and do they all need to transfer data between each other? If the devices do not all need to share data, then start out simpler, eg. design a board with a one channel ADC and one channel DAC, or perhaps dual channels. Even if the ADCs/DACs do need to communicate, consider using a high-speed backplane, or SERDES links (if the ADCs/DACs don't use them all).
Have you looked around to see what commercial boards exist? Would the Altera HSMC boards work, or perhaps one of the Altera DSP kits? You could use that to see if the ADCs/DACs on those boards are adequate for your needs. Then there are devices from companies like Bittware: http://www.bittware.com/products/prodfam.cfm They have Altera FPGA boards and ADC/DAC boards. I haven't used their boards, but would if I had an application that needed them. What signal processing needs to be performed with these boards? Cheers, DaveHonored ContributorSounds like a difficult project. The hardest thing in mixed signal design is to keep the digital noise out of your analog components. I can give you a few hints, but this really requires a good board layout and much experience to do really well.
1) Use linear power supplies and make the supplies for the analog section separate from the digital power. Separate analog and digital circuitry on your board. 2) Edge times on signals is the most important for noise. Altera has programmable slew rates, current and source termination. Use them all. I really recommend using small value resistors like source termination to control edge times. It also provides some isolation from your analog circuitry. 3) The jitter on your oscillator will drive the noise flow of your design. Buy a very low noise oscillator, and use a ferrite bead and caps to isolate the power. It is a noise source. Also use low noise buffer to send oscillator to all of your converters. 4) The PLL's in the FPGA will be all over your system for noise. Make sure the power for these is also isolated like the oscillator, and better yet try not to use them in your design. 5) You can use the memory tool function in Quartus to capture the ADC data for evaluation. Analog devices has a nice tool for evaluating your ADC performance. 6) Make sure that all analog signals are over the analog ground plane. Make sure that the digital control signals enter the analog circuitry at one point for each of the converters. 7) Use signal integrity tools if you have them. Otherwise it may require several board spins to achieve the required noise floor.
