Advice needed on Cyclone III configuration

You can simply assume, that MSEL[3] is tied to 1, if it's not exposed at the package you are using (it has a pull-up, and the chip doesn't know, what package it has been put in). So what do you see in the table?

"Fast" POR modes are only relevant for applications that require to minimize the reset sequence. They don't affect the configuration speed itself. As discussed in the hardware handbook, problems can occur e.g. with non-monotonic supply voltages ramps. Obviously, they are more likely with fast POR. You are asking, why the specification requires a maximum supply ramp time. The handbook doesn't exactly tell. But as a simple explanation, consider the fact, that it's difficult to reproduce exact POR thresholds with basically digital chip technology. A simple solution is to use a lower threshold and specify a safety margin at the time scale.