Advantages of LPM_COMPARE vs. LPM_XOR vs. XOR when comparing two 32 bit numbers

FPGAs do not implement logic as gates but realises it in LUTs. Modern fpgas have aluts(adaptable) e.g. with 6 inputs. Thus if you just write in vhdl:

out <= '1' when a = b else '0';

then this possibly translates to aluts as follows:

6 inputs alut is fed with 3 bits of (a) and 3 bits of (b) and resulting bit is configured in the alut locations according to equality. Thus 64/6 => 11 aluts are needed for first check. the 11 outputs are then checked again in cascade needing 11/6 => 2 aluts and a finl alut makes it 14 aluts overall.

if you use lpm_comapre then it tests more but if only use equality output then it will reduce to 14 aluts I believe.