Honored Contributor
Honored ContributorWhen programming FPGAs, you pretty much have to "try it and see".
You might like to think in terms of XOR, AND, NAND, etc gates, but FPGAs don't really care about them. They care about mapping logic into their look-up tables (LUT), logic elements (LEs), or Adaptive Logic Modules (ALM), whatever the manufacturer has decided to call them. For example, if I want to implement a huge multiplexer (implemented using lots of small muxes), and the FPGA has a 4-input LUT, and I want maximum speed, so plan on pipelining the multiplexer, then I know the "best" I can do is a 2:1 mux, since it has 3 inputs, i.e., the 2 input signals and the select. However, when I move to a different FPGA that has a 6 input LUT, I can create a 4:1 mux, since it has 6 inputs, i.e., 4 input signals and a 2-bit select. Whether or not you use Altera's IP depends on whether you need to "encourage" the logic to use fast carry-chain resources (or some other secret-sauce resource). In the case of a compare, I would expect "if (a==b)" to work just as well as any alternative you can come up with. Don't trust me though, try it yourself, look at the resource usage, and look at the RTL viewer to see how Quartus draws the circuit! :) Cheers, Dave
