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Altera_Forum's avatar
Altera_Forum
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9 years ago

Addition wrong Values, DE1-SoC

Hi, I have the De1-SoC board. I wanted to implement an adder on fpga. The data are on the DDR3 of the HPS. I get access to them with a MSGDMA, what is controlled by the HPS. That works fine...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

If that's all your code, the mistake is to connect to the data line of the streaming interface without providing any handshake. 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Addition is
generic ( Number_of_Taps : integer := 2);
	PORT ( 		
		clk 		: in std_logic;
		reset 	: in std_logic;
		
		inDATA 	:  in std_logic_vector (15 downto 0);
		outDATA	: out std_logic_vector (15 downto 0)
		);
end Addition 
architecture rtl of Addition is
begin
  outDATA <= std_logic_vector(signed(inDATA) + 1);
end architecture;