library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity Addition is
generic ( Number_of_Taps : integer := 2);
	PORT ( 		
		clk 		: in std_logic;
		reset 	: in std_logic;
		
		inDATA 	:  in std_logic_vector (15 downto 0);
		outDATA	: out std_logic_vector (15 downto 0)
		);
end Addition 

architecture rtl of Addition is

begin

outDATA <= std_logic_vector(signed(inDATA) + 1);

end architecture;