adding ddr2 controller to sopc

Hi shamlo,

which development kit are you working with ?

If it is an old one, why don't go on working with an old version of Quartus II ?

Plus, you could find some example designs to use memories in your dev kit.

If your ip was built in sopc, you should upgrade it to work with Qsys. SOPC doesn't exist anymore in latest Quartus versions...

regards,

We r using dsp kit EP2C70F672C6. It comes with quartus II virsion 6. virsion 6 does not have vga and ddr2 controller. So taking this in consideration we r started using 7.2 virsion. It has ddr2 controller suitable for our kit. But it does not contain vga controller. Now our sir told us to use virsion 13 becoase it comes with VIP CORE which we will require for further processing.

So we drop out 7.2 and we moved to 13 virsion. We r facing same vga and ddr2 controller problem in that also. Please suggest some idea to include both controller in virsion 13

http://www.altera.com/products/devkits/altera/kit-dsp-2c70.html?gsa_pos=3&wt.oss_r=1&wt.oss=ep2c70f672c6%20kit

Please visit this link for further details of kit.

shamlo,

why don't you try to generate a new ddr2 controller with Qsys (ALTMEMPHY or UniPHY) ?

(PS : read your messages, I've read your kit's docs)

hi

i am new to using quartus v13.0. i wanna build a video interfacing system using dsp cyclone 2 ep2c70f672c6. to create a core in sopc builder in quartus 2 v13.0 i cant find vga controller for engaging it to fpga. my initial aims are to:

1. engage sd ddr2 ram mt4htf3264ay to fpga.

2. engage vga conroller to fpga.

3. using i2c controller to control image sensor module which is c3038.

pls can some1 help in or direct me how to go about it and help in finding vga controller

we r trying to use the vga controller of ep2c35 to our ep2c70f672c6. Try to help us while making changes in vga controller so that we could use it for EP2C70F672C6

I may contact u for ur help please help us

we r running ddr2 controller in quartus 9 we r getting these eror

Error: Following DDIO Output nodes could not be placed by the Fitter

Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" could not be constrained to a legal location

Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_H[0]" could not be constrained to a legal location

Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|muxa[0]" could not be constrained to a legal location

Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ddio_bidira[0]" could not be constrained to a legal location

Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" could not be constrained to a legal location

Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_H[0]" could not be constrained to a legal location

Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|muxa[0]" could not be constrained to a legal location

Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ddio_bidira[0]" could not be constrained to a legal location

Error: Can't fit design in device

Error: Quartus II Fitter was unsuccessful. 10 errors, 4 warnings

Error: Peak virtual memory: 252 megabytes

Error: Processing ended: Wed Dec 18 16:46:36 2013

Error: Elapsed time: 00:00:05

Error: Total CPU time (on all processors): 00:00:05

shamlo,

Did you correctly assigned all the I/O pins of your ddr2 ?

check them with the reference manual.

(may be wrong device selection in the device settings)

Plus, if your ddr2 controller IP has a .tcl file for further constraints,

don't forget to launch it before fitting the design.

regards,