Honored Contributor
Honored Contributorwe r running ddr2 controller in quartus 9 we r getting these eror
Error: Following DDIO Output nodes could not be placed by the Fitter Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" could not be constrained to a legal location Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_H[0]" could not be constrained to a legal location Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|muxa[0]" could not be constrained to a legal location Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ddio_bidira[0]" could not be constrained to a legal location Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" could not be constrained to a legal location Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_H[0]" could not be constrained to a legal location Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|muxa[0]" could not be constrained to a legal location Error: DDIO Node "hello11:inst1|ddr2_sdram_component_classic_0:the_ddr2_sdram_component_classic_0|ddr2_sdram_component_classic_0_auk_ddr_sdram:ddr2_sdram_component_classic_0_auk_ddr_sdram_inst|ddr2_sdram_component_classic_0_auk_ddr_datapath:ddr_io|ddr2_sdram_component_classic_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ddio_bidira[0]" could not be constrained to a legal location Error: Can't fit design in device Error: Quartus II Fitter was unsuccessful. 10 errors, 4 warnings Error: Peak virtual memory: 252 megabytes Error: Processing ended: Wed Dec 18 16:46:36 2013 Error: Elapsed time: 00:00:05 Error: Total CPU time (on all processors): 00:00:05
