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Altera_Forum's avatar
Altera_Forum
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12 years ago

Adding a vectored interrupt controller has caused the UART module to stop responding

First, I have a system that is made up of a Nios II/e CPU, JTAG debugger UART, interval timer (sys_clk_timer) and a separate UART module that is used for RS232 serial communication, ect. The system w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The altera UART component should de-assert the transmit ready signal (7th bit in the status register) if the FIFO is full, but the signal never turns off.

I originally had it set where I created a pointer to the UART:

while(!pUART->Status.sBits.trrdy); //wait for transmit ready

pUART->TxDATA = myChar; //then transmit data

maybe this is why Altera recommends to use the HAL library functions instead of direct access.