ADC Timing Constraints

I feel like I see this question over and over, but can't quite figure out the answer.

I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use to clock an ADC (ADS831). I sketched out a quick schematic showing what I'm talking about; the attached .gif. The Tcko on the ADC831 is 3.9-12 ns.

I've got the following constraints in my SDC file:

create_generated_clock -name adc_clk -source   -divide_by 2 
#  ADC Input
set_input_delay -clock adc_clk -max 12.0 ] 
set_input_delay -clock adc_clk -min 3.9  ] 
set_multicycle_path -setup -end -from    -to   2
set_multicycle_path -hold  -end -from    -to   1

These constraints seem to be almost right, except I'm getting the always popular "Warning: No paths exist .... Assuming zero source clock latency." problem.

I've got Rysc's User Guide and Source-Synchronous Timing guides up, as well as the Timequest Cookbook and the API, and I've got to say I'm still stumped. Can anyone see what I'm missing here?