Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorADC Timing Constraints
I feel like I see this question over and over, but can't quite figure out the answer. I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use ...
Altera_ForumHonored Contributor
Honored ContributorClocks don't propagate through FFs. You'll need two generated clocks, something like so:
create_generated_clock -name tff_clk -source [get_ports {CLK_125_IN}] -divide_by 2 [get_keepers {*inst3*}] create_generated_clock -name adc_clk -source [get_keepers {*inst3*}] [get_ports {ADC_CLK}]
