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Altera_Forum's avatar
Altera_Forum
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14 years ago

ADC output from LVDS deserializer.

Hi, I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I think you are on a wrong direction. I have used 50MHz, 200MHz, 400MHz ADCs and CycloneIII. The speed of the FPGA is enough. I have met your problem too.

From the AdcOut pciture, the spurs are always on the same positions. That means that one or two bits of AD data are wrong. Analysis the raw data, you will find wrong bits. I think the 2MSB and 4MSB are wrong.

I think the problem is the wire length on PCB is mismatched.

Also, maybe the KEY[0] signal is not needed.

If you tell the ADC kind, it will be helpful.