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Refer to figure 8 in the ADC Timing section of the <DELTED>.
What you've instantiated there is essentially what results having configured the IP from the catalogue into 'Configuration 4: ADC Control Core Only'. Refer to section 2.2.1 "Altera Modular ADC IP Core Configuration Variants", in the same document.
Cheers,
Alex
Edit
**Sorry - need to acknowledge that's exactly what you said you did...
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For some reason I am having a hard time replying with a quote...
This isn't exactly correct. ADC Control Core Only does implement a FSM and FIFO to support the Avalon-ST command/control interface. I am really looking for information on the raw control signals to the ADC block.
Honored Contributor
