ADC Hard Block primitive

Hi Sam,

Hi Tricky,

I think the key line from the user guide is:

Hi Tricky & Alex,

Instantiating isn't really the problem... I dug through the output of the "megawizard" or whatever that thing is called. Here is how you instantiate it in VHDL:

    component fiftyfivenm_adcblock
        generic(
                -- 3-bits 1st stage clock divider.
            -- 0..5 = DIV by 1/2/10/20/40/80;
            -- 6..7 = invalid
            clkdiv : integer := 0;
            
            -- 2nd stage clock divider.
            -- 0 = DIV by 10;
            -- 1 = DIV by 20
            tsclkdiv : integer := 0;
            
            -- 0 = Use 1st stage clock divider when TSEN.
            -- 1 = Use 2nd stage clock divider when TSEN.
            tsclksel : integer := 0;
            
            -- 2-bits To enable the R ladder for the prescalar input channels.
            -- 00 = disable prescalar for CH8 and CH16 (CH8 for device with 2nd ADC)
            -- 01 = enable prescalar for CH8 only
            -- 10 = enable prescalar for CH16 only (CH8 for device with 2nd ADC)
            -- 11 = enable prescalar for CH8 and CH16 (CH8 for device with 2nd ADC)
            -- please note that this is not supported in VR mode
            prescalar : std_logic_vector(1 downto 0) := "00";
            
            -- Reference voltage selection for ADC.
            -- 0 = external;
            -- 1 = internal VCCADC_2P5
            refsel : integer := 0;
            
            -- Ordering Part Number 10MXX... code
            device_partname_fivechar_prefix : string := "10M04";
            
            -- Some part have two ADC, instantiate which ADC?  1st or 2nd?
            -- Valid options: 1 or 2
            is_this_first_or_second_adc : integer := 1;
            
            -- 16 bits to indicate whether each of the dual purpose analog input pin (ADCIN) is in use or not.
            -- 1 bit to indicate whether dedicated analog input pin (ANAIN) is in use or not (bit 16) 
            analog_input_pin_mask : integer := 0;
            
            -- Power Down. Use to disable the ADC during compilation time if no ADC is in use.
            hard_pwd : integer := 0;
            -- Logic simulation parameters which only affects simulation behavior
            enable_usr_sim : integer := 0;
            reference_voltage_sim : integer := 65536;
            simfilename_ch0 : string := "simfilename_ch0";
            simfilename_ch1 : string := "simfilename_ch1";
            simfilename_ch2 : string := "simfilename_ch2";
            simfilename_ch3 : string := "simfilename_ch3";
            simfilename_ch4 : string := "simfilename_ch4";
            simfilename_ch5 : string := "simfilename_ch5";
            simfilename_ch6 : string := "simfilename_ch6";
            simfilename_ch7 : string := "simfilename_ch7";
            simfilename_ch8 : string := "simfilename_ch8";
            simfilename_ch9 : string := "simfilename_ch9";
            simfilename_ch10 : string := "simfilename_ch10";
            simfilename_ch11 : string := "simfilename_ch11";
            simfilename_ch12 : string := "simfilename_ch12";
            simfilename_ch13 : string := "simfilename_ch13";
            simfilename_ch14 : string := "simfilename_ch14";
            simfilename_ch15 : string := "simfilename_ch15";
            simfilename_ch16 : string := "simfilename_ch16"
        );
        port(
                chsel : in std_logic_vector(4 downto 0);        -- 5-bits channel selection.
                soc : in std_logic;                    -- signal Start-of-Conversion to ADC                                    
                eoc : out std_logic;                    -- signal end of conversion. Data can be latched on the positive edge of clk_dft after this signal becomes high.  EOC becomes low at every positive edge of the clk_dft signal.
                dout : out std_logic_vector(11 downto 0);    -- 12-bits DOUT valid after EOC rise, still valid at falling edge, but not before the next EOC rising edge
                usr_pwd : in std_logic;                    -- User Power Down during run time.  0 = Power Up;  1 = Power Down.                                
                tsen : in std_logic;                    -- 0 = Normal Mode; 1 = Temperature Sensing Mode.                                 
                clk_dft : out std_logic;                    -- Output clock from the clock divider
                clkin_from_pll_c0 : in std_logic            -- Clock source from PLL1 c-counter at BL corner or PLL3 c-counter at TL corner
            );
    end component;

Have you tried contacting Altera via mysupport? often, specific questions get you through directly to the correct support people, who can either provide the docs or tell you how to drive it.

Refer to figure 8 in the ADC Timing section of the "max® 10 analog to digital converter user guide (http://max® 10 analog to digital)".