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Altera_Forum's avatar
Altera_Forum
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16 years ago

Accelerate design performance

Hi, I found a very interesting White Paper from Xilinx "HDL Coding Practices to Accelerate Design Performance" (WP231, you have to search it yourself because I'm not allowed to post links...),...
Altera_Forum's avatar
Altera_Forum
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16 years ago

The synchronous reset recommended by Xilinx seems to be a combined Toolchain+Device issue. If the RTL is ideal, ISE is able to optimise perfectly in some cases.

I think it's very likely that similar optimisations are possible for Quartus+Altera Device but I was unable to find a document about it.