About Transceiver???

Hi kaz, I'm a partner of ztr1918294

Thank you for your kindly and professional answer, we learned a lot from you about transceiver.

I have another question, since the serdes Rx contains a internal PLL which is used to lock the data frequency, it should take some time for PLL to lock to reference data’s frequece, how long is the recovery time?

I want to explain “recovery time” more clearly, Our data stream is a little special, the link will be all “0” when there’s no data, so it is impossible to lock the data frequency for PLL when the link is idle. and the link will be not all “0” until there a data frame transmitted on this link, so I think the PLL needs to relock the data frequecy for every data frame. “recovery time” I want to know is how long the serdes Rx is able to lock to the data’s frequency from a frame starts to transmit on the link

Hi,

You are right, the PLL will need sometime to lock as any PLL(this includes locking to ref clock then recovering data clock, say few microsec). The stream then has to be locked to(depends on how you lock to it, your state machine). You can arrange to monitor these two lock cases.

Equally, you are right, with an all-zero stream you are likely to run into trouble. Why not change the stream to any other fixed but alternating pattern. This also helps keeping locked to stream when idle.

You may wonder how to read valid data then. In my system I allocated many extra bytes at beginning of each packet. One byte was used to indicate the start of first valid byte and another byte to indicate the number of bytes to follow(you don't need this if it is fixed size).

You can add any information in the link as header to packets as long as your link speed is fast enough which I believe it can be e.g. channel number, any user parameters...

By the way, we used this link to pass our channels as well as remotely download all firmware and software to a flash. This is very attractive feature when you can update a buggy program through internet.

Hope this helps.

Kaz

I am so grateful for your quick answers.

Actually we are carrying out a research on optical network technology called Optical Burst Switched (OBS), one of its features is the data link is not continuous but swiched all the time. for example, there are 3 nodes in an network, called A, B, C. node B and C is connected to node A through a optical switch. the optical switch will continuous change the optical path between A-B and A-C according the setup message, so it is inevitable to relock the data frequence when optical path changed.

therefore the recovery time is essential for our design, I don't know if it is fixed or can be estimated by some method, it will be very helpful if you can share us some material about this parameter.

Many Thanks,

Liming

Hi,

I believe you can measure the lock time directly by using a counter in fpga

that start counting up after a general reset that is applied to the Rx as well as the counter. The counter to stop when lock is flagged by the serdes Rx.

You can see the final counter result directly in a signal tap(ELA/chipscope) then convert it to time.

Remember there are two stages(A PLL lock followed Rx recovery lock which is what need to measure). Use any suitably fast clock for the signal tap counter

Kaz

It may be useful to check the GXB transceiver specification in detail.

The GXB clock recovery unit can be configured to tolerate up to 1000 ppm frequency deviation. If this amount is sufficient for your application, the lock time to phase steps is most likely the most serious issue. I didn't find an explicite CRU lock time specification, but it may be estimated from the maximum receiver PLL bandwidth of 60 MHz.

hello all

Could you please tell if it was successful to use CDR in side the ALtera FPGA to receive the burst traffic .

thank you

Hi all

I have a similar question

I need to design a CDR working at 160 Mbps, +/- 1%

the input frame is NRZ biphase mark: 00110101101001.. ( max 2 consecutive "0" or "1" )

I can do it by using a ADN1814 : http://www.analog.com/en/clock-and-timing/clock-and-data-recoveryretiming/adn2814/products/product.html

but, is it possible to do the same by using the CRD inside transeiver of the ARRIA ?

Thanks in advance for your help

JJ