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testp's avatar
testp
Icon for New Contributor rankNew Contributor
5 years ago
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About the number of PLL outputs （CYCLONE5）

About the number of output pins of the PLL If you check CV-52004 Table 4-7: PLL Features in Cyclone V Devices There is the following description in. Dedicated external clock outputs → 2 sing...
  • Ash_R_Altera's avatar
    Ash_R_Altera
    5 years ago

    Hi,

    The 'nine clock output signals for the Cyclone V devices' in Altera PLL IP core corresponds to

    C output counters -> 9

    in the Cyclone V handbook. These are the clocks generated from the PLL.

    The Dedicated external clock outputs represent the FPLL_<#>_CLKOUT pins on the device. You can connect any of the C output counters to external clock outputs. Refer 4.2.6. PLL External Clock I/O Pins of Device Handbook.

    There are dedicated clock output pins associated with each corner fractional PLL.


    So the main difference is that C counters are PLL outputs (internal to FPGA) whereas CLKOUT pins are device outputs (available external to the FPGA).


    Regards



Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

The 'nine clock output signals for the Cyclone V devices' in Altera PLL IP core corresponds to

C output counters -> 9

in the Cyclone V handbook. These are the clocks generated from the PLL.

The Dedicated external clock outputs represent the FPLL_<#>_CLKOUT pins on the device. You can connect any of the C output counters to external clock outputs. Refer 4.2.6. PLL External Clock I/O Pins of Device Handbook.

There are dedicated clock output pins associated with each corner fractional PLL.


So the main difference is that C counters are PLL outputs (internal to FPGA) whereas CLKOUT pins are device outputs (available external to the FPGA).


Regards