About the cycloneIII IO output speed

Jitter can be generally expected to be lower with differential I/O standard. The ADC clock input can be possibly also driven from a single ended output not exactly complying LVTTL or LVCMOS IO specifications, you should should check the datasheet details. But a differential connection is surely less susceptible to common mode noise, which is most likely the dominant jitter source. Unfortunately, also the FPGA input clock jitter is critical in this respect, so you may want to use a differential interface for minimum jitter in this place, too.