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Altera_Forum's avatar
Altera_Forum
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16 years ago

About the cycloneIII IO output speed

hi everybody I'm trying to use the EP3C25F324C8 to generate 250MHz clock as high speed AD（AD9481） clock，could it work？I don't know if the user IO (3V3 LVTTL)or PL...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Assuming that you successfully manage to generate a 250MHZ clock in your FPGA then 250MHz is probably too fast for LVTTL outputs.

Consider using differential LVDS or similar standards for output pins