Forum Discussion

drli's avatar
drli
Icon for New Contributor rankNew Contributor
3 years ago

About PCIE problems

I design a board using FPGA Arria 10AX016E4F27E3SG serving as an endpoint in PCIE 2.0. The board communicates with the PCIE switch plugged on PC's PCIE slot through fiber and SFP+ optical module. Whe...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


I suggest you to try use logic analyzers to capture and analyze digital signals in your design. This can help you identify issues with signal timing or protocol compliance.


Hope that helpful.

Regards,

Wei Chuan