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wzhen25's avatar
wzhen25
Icon for New Contributor rankNew Contributor
6 years ago

About LVDS SERDES Intel FPGA IP(Stratix 10)

In recent, I 'm working a project that requires LVDS receiver, and the LVDS receiver needs be configured to external PLL mode and DPA mode. When I set the parameter "reference clock" of the external...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Just to make sure what I understood from your statement is , with 100 MHz reference clock on PLL everything working fine , but when you change the reference clock to 333.33 MHz ; dpa_locked is not asserting after pll_locked assert ,correct ?

Are you using eval board or custom board ? if you have a eval board can you check once ?

Thank you ,

Regards,

Sree