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wzhen25's avatar
wzhen25
Icon for New Contributor rankNew Contributor
7 years ago

About LVDS SERDES Intel FPGA IP(Stratix 10)

In recent, I 'm working a project that requires LVDS receiver, and the LVDS receiver needs be configured to external PLL mode and DPA mode.

When I set the parameter "reference clock" of the external PLL to 100MHz, the LVDS receiver works well. But once I set the parameter to 333.333333MHz, the port "dpa_locked" of the LVDS receiver can never assert after the port "ext_pll_locked" asserts.

Does anybody know the reason? Thanks a lot!

1 Reply

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Just to make sure what I understood from your statement is , with 100 MHz reference clock on PLL everything working fine , but when you change the reference clock to 333.33 MHz ; dpa_locked is not asserting after pll_locked assert ,correct ?

    Are you using eval board or custom board ? if you have a eval board can you check once ?

    Thank you ,

    Regards,

    Sree