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Altera_Forum
Honored Contributor
18 years agoAbout DK-N2EVAL-3C25N
Hi there.
I've purchased DK-N2EVAL-3C25N and tried to compile samples such as cycloneIII_3c25_start_my_first_fpga.qpf via Quartrus 7.2 but with no success. Error: Missing required positional arguments: <delay>, <targets> --------------------------------------------------------------------------- Usage: set_output_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets> -h | -help: Short help -long_help: Long help with examples and possible return values -add_delay: Add to existing delays instead of overriding them -clock <name>: Clock name -clock_fall: Specifies output delay relative to the falling edge of the clock -fall: Specifies the falling output delay at the port -max: Applies value as maximum data required time -min: Applies value as minimum data required time -reference_pin <name>: Specifies a port in the design to which the output delay is relative -rise: Specifies the rising output delay at the port -source_latency_included: Specifies input delay already includes added source latency <delay>: Time value <targets>: Collection or list of output ports --------------------------------------------------------------------------- while executing "set_output_delay -clock [get_clocks {pll:inst1|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]}] " (file "C:/altera/72/kits/cycloneIII_3c25_niosII_eval/examples/my_first_fpga/cycloneIII_3c25_start_my_first_fpga.sdc" line 47) Even though I didn't modify anything at all but with no luck. Does anyone know how to solve this problem. Thanks.4 Replies
- Altera_Forum
Honored Contributor
Hi michael.d.miller.
Thank you for your throwing request on the issue. - Altera_Forum
Honored Contributor
I opened a service request on the issue. Hopefully that should get it fixed.
Regards, Mike - Altera_Forum
Honored Contributor
>The root of the problem is that the .sdc file has line terminators with \r,
Your comment made it possible to compile. Thanks a lot. I hope that Altera fixed the problem. How could we tell Altera about it ? - Altera_Forum
Honored Contributor
I'm surprised that no one replied to this and that Altera is still shipping files with this problem even in version 8 of the DSP builder kit. The root of the problem is that the .sdc file has line terminators with \r, which breaks the continuation processing for some of
the directives in the .sdc. These can be edited if you have an editor that shows line terminations, such as Vim (:s/\r//g).