Forum Discussion

SiWu's avatar
SiWu
Icon for New Contributor rankNew Contributor
3 months ago

about cyclone 10gx transceiver

Hi, recently I am trying to debug cyclone 10 gx transceivers, and the settings are as the figures above. After reseting, I first send 32'h12345678...
Core Logic
Generic Io
Programmable Logic Device
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
3 months ago

Also, just to make sure I am clear, expected settings 

 

ON RX SiDE

RX FIFO mode = Phase compensation 
Enable block sync = ON 
Enable rx_enh_blk_lock = ON 
Enable rx_bitslip = optional (not needed anymore)

 

 

SiWu's avatar
SiWu
Icon for New Contributor rankNew Contributor
3 months ago

Thank you for you reply. But unfortunately, when I enable Rx block synchronizer, error appear, as shown in the following figure.

 

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi,

    The Rx block synchronizer works when 'Enhanced PCS/PMA interface width' = 40 or 64, 'FPGA fabric / Enhanced PCS interface width' = 66 and 'Enable RX data bitslip' = Unchecked.

    Please try these settings.

     

    Regards

    • SiWu's avatar
      SiWu
      Icon for New Contributor rankNew Contributor
      2 months ago

      Thanks a lot for your reply. From your description, can I say that when 'Enhanced PCS/PMA interface width' = 32, there is no way to send and receive data correctly?

      • Ash_R_Altera's avatar
        Ash_R_Altera
        Icon for Regular Contributor rankRegular Contributor
        2 months ago

        For your original settings with 'Enhanced PCS/PMA interface width' = 32. Try changing the Enhanced PCS RX FIFO mode to Register instead of phase compensation mode.

         

        Regards