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Honored Contributor
Honored Contributorabout "create a clk in TA"
I used some wire or register to be a clk . but i dont assign a clk attribute to it in TA, so i get warning "Warning: Node: global_reset:u7|byte_read_clk was determined to be a clock but was found wit...
Altera_ForumHonored Contributor
Honored Contributorthanks very much !
yes,gated clock may have problem within FPGAs? you mentioned that there is an option to used clock enables ,do you mean that use a PLL enable to control the generation of clock .
