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Honored Contributor
Honored Contributorabout "create a clk in TA"
I used some wire or register to be a clk . but i dont assign a clk attribute to it in TA, so i get warning "Warning: Node: global_reset:u7|byte_read_clk was determined to be a clock but was found wit...
Altera_ForumHonored Contributor
Honored ContributorThe tools need timing information. If you don't provide a clock constrain, the tools will just assume a 1 GHz clock.
You should create a clock constrain, as close to your real clock as possible. For example, ignore the fact that it's gated (muted) and just specify it's base frequency. Gating clocks within FPGAs has issues; if possible, it's best to replace gated clocks with clock enables.
