About configuration in AS mode

Hi Yamada1,

You can refer to the user guide under sub-topic 7.2.1.1. DATA Clock (DCLK) on page 227 in the Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook. It does mention that the Arria 10 devices drive control signals on the falling edge of DCLK and latch the configuration data on the following falling edge of this clock pin. You can source DCLK using CLKUSR or the internal oscillator.

You can refer 7.3.2. CLKUSR on page 249 for additional explanation on CLKUSR. I hope this would clarify your concern

Regards,

Fakhrul