about component

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity mand2 is

port(

a,b:in std_logic;

c:out std_logic);

end mand2;

architecture bb of mand2 is

begin

c<=a and b;

end bb;

use work.mand2.all;

library ieee;

use ieee.std_logic_1164;

entity p60 is

port(x,y:in std_logic;

z:out std_logic);

end p60;

architecture b of p60 is

component mand2

port(a,b:in std_logic;

c:out std_logic);

end component;

begin

mand2 port map(a=>x,b=>y,c=>z);

end b;

Error (10500): VHDL syntax error at p60.vhd(14) near text "port"; expecting "(", or "'", or "."

i really can't understand that error.