Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorabout component
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mand2 is port( a,b:in std_logic; c:out std_logic); end mand2; architecture bb of mand2 is begin ...
Altera_ForumHonored Contributor
Honored ContributorAll the questions you have easily find an answer in any VHDL book... to instantiate a component the syntax is:
Label: componentName generic map (...) port map (...);
