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JET60200's avatar
JET60200
Icon for Contributor rankContributor
4 years ago

A10 PCIe HIP "nreset_status" signal tobe deasserted randomly, even though npor&pin_pers remains high

hello expert, We uses Arria10 PCIe HIP core to build a EP device. In general, the FPGA works fine when plugging inside x86 SERVER PCIE Slot at most cases . But for a part of x86 servers, we f...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY