Forum Discussion

JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago

A10 PCIe HIP "nreset_status" signal tobe deasserted randomly, even though npor&pin_pers remains high

hello expert, We uses Arria10 PCIe HIP core to build a EP device. In general, the FPGA works fine when plugging inside x86 SERVER PCIE Slot at most cases . But for a part of x86 servers, we f...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Does the transceiver calibration successful? Can you check if the pin_perst of the Hard IP instance connects to the corresponding nPERST pin of the device correctly? Could you share the signal tap result?


These pins have the following locations:

• NPERSTL0: bottom left Hard IP and CvP blocks

• NPERSTL1: top left Hard IP block

• NPERSTR0: bottom right Hard IP block

• NPERSTR1: top right Hard IP block


Thanks

Best regards,

KhaiY