Forum Discussion

JET60200's avatar
JET60200
Icon for Contributor rankContributor
6 years ago

A10 AVMM DMA has only a single MSI to Host, how to distinguish this DMA completion is from READ DMA controller, or from WRITE DMA controller?

hi everyone, ​ I'm using Arria10 which is PCIe EP in X86 Host. Per my understanding, Altera AVMM-DMA only provides single MSI to notify the DMA is completion(both READ DMA controller and WRITE DMA ...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Yes, page 81 explains the behavior of multiple writes to the LAST_PTR. You can also refer to page 82, the description of RDDMA_LAST_PTR for more definition.

Regards -SK