A10 AVMM DMA has only a single MSI to Host, how to distinguish this DMA completion is from READ DMA controller, or from WRITE DMA controller?

Hi SK,

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I'm checking A10 AVMM DMA reference linux driver code (gen3x8_avmm_dma_Linux), in " altera_dma.c " file -> dma_test() function, there are below code :

last_id = last_id + bk_ptr->dma_status.altera_dma_descriptor_num; /// calculate to get new "last-id" param

if(last_id > 127){

last_id = last_id - 128;

if((bk_ptr->dma_status.altera_dma_descriptor_num > 1) && (last_id != 127)) write_127 = 1; /// check whether "last-id" roll back to "descriptor[] head"

}

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if(write_127) iowrite32 (127, bk_ptr->bar[0]+DESC_CTRLLER_BASE+ALTERA_LITE_DMA_RD_LAST_PTR); /// (--- 1 )

iowrite32 (last_id, bk_ptr->bar[0]+DESC_CTRLLER_BASE+ALTERA_LITE_DMA_RD_LAST_PTR); /// (--- 2 )

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Here to my understand it write "id" into LAST_PTR to start DMA operation. But why can the "LAST_PTR" be be written twice continueously ?

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To my understanding, the second iowrite32 (last_id, .. ) will overwrite the first iowrite32 (127, ..).

Does DMA Controller support the sequence writing : iowrite32 (a,) -> iowrite32 (b,) -> iowrite32 (c,) -> iowrite32 (d,) .. And still keep running correctly ?

Can you clarify a bit. Thanks

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In https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf, there are sentence in page 81 as following :

" .. host software should write multiple IDs into the last pointer register. as example :

1. Program the RD_DMA_LAST_PTR = 63.
2. Program the RD_DMA_LAST_PTR = 127.
3. Poll the status DWORD for read descriptor 63.
4. Poll the status DWORD for read descriptor 127

"

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Does this explain it from Intel perspective ? ​

Thanks