A very simple problem about FPGA I/O Status

Hi anakha,

Your opinion on optimization is correct. I tried to initialize as:

reg Start_Detect = 0;

assign Start_Detect_LED = Start_Detect;

always @(posedge CLK)

begin

Start_Monitor[0] <= Start;

Start_Monitor[3:1] <= Start_Monitor[2:0];

Start_Flag <= (Start_Monitor[3]&(~Start_Monitor[2]));

if(Start_Flag == 1)

Start_Detect <= 1;

end

This code worked as expected. So it seems that uninitialized register would cause this kind of 'Optimization' problem.

But this is pretty wired to me. Why the Optimization (done by Quartus) is designed like this? Can I bypass this kind of optimization?

Thanks~~