A very simple problem about FPGA I/O Status

The reason would be how the logic is optimized.

In your previous design with the timer, the logic may be high or low or unknown. So the design happens to get initialized as zero, and it works as you expect it to.

When you change the design so your timer is removed you are also removing the only thing that can set the LED to off. So all the start logic gets optimized out because your only possible states on your LED are on or unknown. Since it doesn't care about the "Unknown" state in the optimization, it will just end up tying the LED to on.

Now although your designed worked, in your case in practice and simulation having uninitialized counters and outputs can cause problems.

I would recommend having a reset in the design, or at the very least having the counter start with the push button at a known count then count down to zero.

If you tried to simulate this design, all you would get at the output would be X's because the initial state of your counter is unknown, so adding 1 to an unknown is still an unknown.

How this would manifest itself in an ASIC, is the first time the button was pushed your delay would not be random.

In an FPGA it would most likely be consistent but it may that the counter gets initialized as all zero's or all one's as the devices is programmed.

Pete