A very basic newbie question

Hi All

I have a very basic question. I've recently started learning about CPLD and VHDL. My VHDL code usually compiles and simulates fine, but when I put it in an actual CPLD it behaves really strange. I'm sure you have all been there. Could you please solve this mystery for me?

Basically what I am doing is dividing the global clock by 500, and incerementing a counter to show the value on a seven segment. This is the very simple code, I am using MAX EPM7128SLC84-15:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
-- this is the entity
Entity V2 Is
 Port ( 
  GClk : In std_logic; --Global clock, pin 83
  SS : Out std_logic_vector(6 Downto 0); -- Connected to the Seven Segement
   );
End V2;
 
Architecture RTL of V2 is  
 Signal MyClk : std_logic;      -- The divided clock
 Signal SevSegVal : std_logic_vector(6 downto 0);
Begin 
 Process (GClk)
  Variable Count : Integer Range 0 To 1023 := 0;
 Begin
  If (rising_edge(GClk)) Then
   Count := Count + 1;
   If (Count = 500) Then
    Count := 0;
    MyClk <= Not MyClk;
   End If;
  End IF;
 End Process;  
 
 
 PROCESS (MyClk)
  Variable Counter : Integer Range 0 To 9 := 0;
  Type SSValues Is array(integer range 0 to 9) Of std_logic_vector(6 downto 0); 
  Variable  Values : SSValues := (('1', '0', '0', '0', '0', '0', '0')
        , ('1', '1', '1', '1', '0', '0', '1')
        , ('0', '1', '0', '0', '1', '0', '0')
        , ('0', '1', '1', '0', '0', '0', '0')
        , ('0', '0', '1', '1', '0', '0', '1')
        , ('0', '0', '1', '0', '0', '1', '0')
        , ('0', '0', '0', '0', '0', '1', '0')
        , ('1', '1', '1', '1', '0', '0', '0')
        , ('0', '0', '0', '0', '0', '0', '0')
        , ('0', '0', '1', '0', '0', '0', '0'));  -- To hold the bit pattern for the seven segment numbers
 
 Begin  
  If (rising_edge(MyClk)) Then
   SevSegVal <= Values (Counter);
   If (Counter = 9) Then
    Counter := 0;
   Else
    Counter := Counter + 1;
   End IF;
  End If;
 End Process;
 
 SS <= SevSegVal;
 
End RTL;

This code simulates fine in Quartus II using a vector waveform file. But doesn't work properly when I upload it to my development board.

The problem is the the seven segment flickers. I can see it count, but the lamps that are supposed to be off for each number flicker dimly.

From what I can see, Quartus II (v 8.0) synthesizes this code to a latch which is clocked by MyClk, which goes to high impedance during the wait and causes the lines to float and flicker. Am I right?

To me, it seems I am violating some 'well-known' rules for writing synthesizable code that actually works in real hardware. What am I doing wrong? What is the correct way of dividing a clock and incrementing a seven segment counter? I really really appreciate your help.