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The Count and Counter in the RTL represent actual objects (FFs) in real design, so you must declare them as signal and use <= instead of :=.
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I don't agree. The variables are effectively treated by Quartus as signals here. A different behaviour is only in cases, when the variable is used in other expressions after assigning a new value. The Quartus VHDL templates are showing the same counter style, BTW.
The design uses a
ripple clock, which would cause timing issues if the primary GCLK shall be used in connection with the derived MyClk. Cause both clock domains are strictly separated, it's O.K.
The RTL view looks O.K., the Technology Map is somewhat
special with MAX7000, but seems to represent a meaningful synchronous design, as expectable from the code.
May it be the case, that your input clock is simply too fast to view anything?
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