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Honored Contributor
Honored ContributorA very basic newbie question
Hi All I have a very basic question. I've recently started learning about CPLD and VHDL. My VHDL code usually compiles and simulates fine, but when I put it in an actual CPLD it behaves really...
Altera_ForumHonored Contributor
Honored ContributorHi,
The Count and Counter in the RTL represent actual objects (FFs) in real design, so you must declare them as signal and use <= instead of :=. Thanks
