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Altera_Forum
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17 years ago

A very basic newbie question

Hi All I have a very basic question. I've recently started learning about CPLD and VHDL. My VHDL code usually compiles and simulates fine, but when I put it in an actual CPLD it behaves really...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

The Count and Counter in the RTL represent actual objects (FFs) in real design, so you must declare them as signal and use <= instead of :=.

Thanks