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Altera_Forum's avatar
Altera_Forum
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18 years ago

A very basic newbie question

Hi All I have a very basic question. I've recently started learning about CPLD and VHDL. My VHDL code usually compiles and simulates fine, but when I put it in an actual CPLD it behaves really...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

First of all you may try to down-speed your implementation, as FvM suggests. Go to very low frequencies and check out the result.

Then take care about the current driving the 7-segments modules, be sure that the current (either directly generated by the CPLD or through a buffer) is within the specified acceptable range.