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The design uses a
ripple clock, which would cause timing issues if the primary GCLK shall be used in connection with the derived MyClk. Cause both clock domains are strictly separated, it's O.K.
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Although in principle there is nothing necessarily wrong with using two clocks as you have done, clocks/global signals are generally not in abundance in FPGAs/PLDs. Personally I would generate a clock enable pulse rather than another clock and then use a clock enabled register to drive the display.
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Even though it's apparently not critical for this design, in general you should follow batfink's advice. See
http://www.alteraforum.com/forum/showthread.php?t=2388 for more information about driving clocks with registers or combinational logic versus using the preferred clock enable.
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