a strange problem!

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Hi,I'm sorry! and I forget it .

my <>.qsf is

# --------------------------------------------------------------------------#

#

# Copyright (C) 1991-2009 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors. Please refer to the

# applicable agreement for further details.

#

# --------------------------------------------------------------------------#

#

# Quartus II

# Version 9.0 Build 132 02/25/2009 SJ Full Version

# Date created = 17:02:23 July 13, 2009

#

# --------------------------------------------------------------------------#

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

# zhengxing_assignment_defaults.qdf

# If this file doesn't exist, see file:

# assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

# file is updated automatically by the Quartus II software

# and any changes you make may be lost or overwritten.

#

# --------------------------------------------------------------------------#

set_global_assignment -name FAMILY "Cyclone II"

set_global_assignment -name DEVICE EP2C5T144C8

set_global_assignment -name TOP_LEVEL_ENTITY zhengxing

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:02:23 JULY 13, 2009"

set_global_assignment -name LAST_QUARTUS_VERSION 9.0

set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name VERILOG_FILE zh.v

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"

set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

set_global_assignment -name MISC_FILE "E:/cheng_xu/zhengxing/zhengxing.dpf"

set_global_assignment -name QIP_FILE pll_0.qip

set_global_assignment -name BDF_FILE zhengxing.bdf

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"

set_location_assignment PIN_17 -to clk

set_location_assignment PIN_51 -to data_in

set_location_assignment PIN_48 -to data_out

set_location_assignment PIN_75 -to rst

set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"

set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS1

set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"

set_global_assignment -name VECTOR_WAVEFORM_FILE zhengxing.vwf

set_global_assignment -name SETUP_HOLD_DETECTION ON

set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED ON

set_global_assignment -name SIGNALTAP_FILE stp1.stp

set_global_assignment -name ENABLE_SIGNALTAP OFF

set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp

thank you!

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Hi,

I did not see your verilog file ( in your first post) in the qsf. Are you using the zhengxing.bdf ? Is your reset signal connected ? Polarity ?

Kind regards

Gerd