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Honored Contributor
Honored Contributora strange problem!
module zhengxing(clk_200M, rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low...
Altera_ForumHonored Contributor
Honored ContributorAs a start, for debug purposes, remove or comment out all the logic in the process and just tie your outport to 'low' to see if this pin can toggle.
ie. data_out <- '0'. Observe this at the FPGA out and if this pin is still staying high then check your drive strengths for that pin in your qsf file.
