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Honored Contributor
Honored Contributora strange problem!
module zhengxing(clk_200M, rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low...
Altera_ForumHonored Contributor
Honored ContributorI assume clk_200M is a 200 MHz clock signal. Perhaps this is too fast for the FPGA you are using. Which FPGA and speed grade are you using?
