A simple problem with bidirectional bus in VHDL

The situation is: I have one bidirectional bus and two registers and two buffers tri-state. Just as you can see at this link: @@@@dl.dropbox.com/u/288645/Drawing1.png@@@@

But when I open the simulation in modelsim, I receive a warning message: "Warning: (vsim-8683) Uninitialized inout port /unity/registerA/data(7) has no driver." And the same to all the 8 bits of the bus. I tried a lot of things but I couldn't solve it. Then every time I simulate, the bus stays as "U" uninitialized state. If someone can help me, I'll be very grateful!!

P.S.: Whe I tried with only one register and one buffer tristate, it worked fine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity unity is
    port(data: inout std_logic_vector(7 downto 0);
         loadA,loadB,enA,enB: in bit;
         clk: in std_logic);
end entity;
architecture behavioral of unity is
component tristate
  port(data: out std_logic_vector(7 downto 0);
         data_in: in std_logic_vector(7 downto 0);
         enable: in bit);
end component;
component registrador
  port(lx: in bit;
         clk: in std_logic;
         data: inout std_logic_vector(7 downto 0);
         x: out std_logic_vector(7 downto 0));
end component;
signal out_a,out_b: std_logic_vector(7 downto 0);
begin
  registerA: registrador port map(loadA,clk,data,out_a);
  registerB: registrador port map(loadB,clk,data,out_b);
  bufferA: tristate port map(data,out_a,enA);
  bufferB: tristate port map(data,out_b,enB);
end architecture;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity registrador is
    generic(
        MAX_COUNT: in natural := 8);
    port(lx: in bit;
          clk: in std_logic;
          data: inout std_logic_vector(MAX_COUNT-1 downto 0);
          x: out std_logic_vector(MAX_COUNT-1 downto 0));
end entity;
architecture behavioral of registrador is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if lx = '1' then
                x <= data;
            end if;
        end if;
    end process;
end architecture;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tristate is
    port(data: out std_logic_vector(7 downto 0);
           data_in: in std_logic_vector(7 downto 0);
           enable: in bit);
end entity;
architecture behavioral of tristate is
  begin
    process(enable)
    begin
        if enable = '1' then
            data <= data_in;
        else
            data <= (others => 'Z');
        end if;
    end process;
end architecture;